Programmable Logic Array (PLA)

 

The PLA is similar to PROM in concept except that PLA does not provide full decoding of the variable and does not generate all the minterms . The decoder is replaced by an array of AND gates that can be programmed to generate any product term of the input variables. The product terms are then connected to OR gates to provide the sum of products for the required Boolean functions.

The decoder in PROM is replaced by an array of AND gates that can be programmed to generate any product term of the input variables.

The product terms are then connected to OR gates to provide the sum of products for the required Boolean functions.

The output is inverted when the XOR input is connected to 1 (since x⊕1 = x’). The output doesn’t change and connect to 0 (since x⊕0 = x).

F1 = AB’+AC+A’BC’

F2 = (AC+BC)’

The diagram uses the array logic graphic symbols for complex circuits. Each input goes through a buffer and an inverter shown in the diagram with a composite graphic symbol which has both the true and complement outputs. Each input and its complement are connected to the inputs of each AND gate as indicated by the intersections between the vertical and horizontal lines. The outputs of the AND gates are connected to the inputs of each OR gate.

The output of the OR gates goes to an XOR gate where the other input can be programmed to receive a signal equal to either logic 1 or 0. The

output is inverted when the XOR input is connected to 1. The output does not change when the XOR input is connected to 0 .

The product terms generated in each AND gate are listed along the output of the gate in the diagram. The product term is determined from the inputs whose crosspoints are connected and marked with a X . The output of an OR gate gives the logic sum of the selected product terms. The output may be complemented or left in its true form depending on the connection for one of the XOR gate inputs.

 The programming table that specifies the PLA of Fig.4 is listed in Table 2. The PLA programming table consists of three sections .The first section lists the product terms numerically. The second section specifies the required paths between inputs and AND gates. The third section specifies the paths between AND and OR gates.

A T output dictates that the other input of the corresponding XOR gate be connected to 0,and a C specifies a connection to 1.The size of a PLA is specified by the number of inputs ,the number of product terms and the number of outputs. When designing a digital system with a PLA there is no need to show the internal connections of the units. All that is needed is a PLA programming table from which the PLA can be programmed to supply the required logic.

Programming Table:

1. First: lists the product terms numerically

2. Second: specifies the required paths between inputs and AND gates

3. Third: specifies the paths between the AND and OR gates

4. For each output variable, we may have a T(ture) or C(complement) for programming the XOR gate

Simplification of PLA :

Careful investigation must be undertaken in order to reduce the number of distinct product terms, PLA has a finite number of AND gates.

Both the true and complement of each function should be simplified to see which one can be expressed with fewer product terms and which one provides product terms that are common to other functions.

Example:

Implement the following two Boolean functions with a PLA:

F1(A, B, C) = Σ(0, 1, 2, 4)

F2(A, B, C) = Σ(0, 5, 6, 7)

The two functions are simplified in the maps of Fig.7-15

PLA table by simplifying the function:

Both the true and complement of the functions are simplified in sum of products.

We can find the same terms from the group terms of the functions of F1, F1’,F2 and F2’ which will make the minimum terms.

F1 = (AB + AC + BC)’

F2 = AB + AC + A’B’C’

PLA implementation:

Note that output F1 is the true output even though a c is marked over it in the table. This is because F1 is generated with an AND-OR circuit and is available at the output of the OR gate. The XOR gate complements the function to produce the true F1 output.

The combinational circuit used in this example is too simple for implementing with a PLA.