Programmable Array Logic (PAL)

 

The programmable array logic (PAL) is a programmable logic device with a fixed OR array and a programmable AND array. Because only the AND gates are programmable the PAL is easier to program, but is not as flexible as the PLA.

Figure 5 shows the logic configuration of a typical PAL.

It has four inputs and four outputs. Each input has a buffer inverter gate and each output is generated by a fixed OR gate. There are four sections in the unit, each being composed of a three wide AND-OR array.

Each AND gate has 10 programmable input connections. This is shown in the diagram by 10 vertical lines intersecting each horizontal line. The horizontal line symbolizes the multiple input configuration of the AND gate. One of the outputs is connected to a buffer inverter gate and then fed back into two inputs of the AND gates.

When designing with a PAL, the Boolean functions must be simplified to fit into each section.

Unlike the PLA, a product term cannot be shared among two or more OR gates. Therefore, each function can be simplified by itself without regard to common product terms.

The output terminals are sometimes driven by three-state buffers or inverters.

PAL Example :

w(A, B, C, D) = Σ(2, 12, 13)

x(A, B, C, D) = Σ(7, 8, 9, 10, 11, 12, 13, 14, 15)

y(A, B, C, D) = Σ(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)

z(A, B, C, D) = Σ(1, 2, 8, 12, 13)

Simplifying the four functions as following Boolean functions:

w = ABC’ + A’B’CD’

x = A + BCD

w = A’B + CD + B’D’

w = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D

PAL Table:

z has four product terms, and we can replace by w with two product terms, this will reduce the number of terms for z from four to three.

The table is divided into four sections with three product terms. The first two sections need only two product terms to implement the Boolean function. The last section for output z needs four product terms. Using the output from w, we can reduce the function to three terms.

PAL implementation :

Fuse map for example :

For each 1 or 0 in the table, we mark the corresponding intersection in the diagram with the symbol for an intact fuse. For each dash we mark he diagram with blown fuses in both the true and complement inputs. If the AND gate is not used, we leave all its input fuses intact.

Since the corresponding input receives both the true and complement of each input variable we have AA’=O and the output of the AND gate is always O.