Parity Checker/Parity Generator

Parity generation is one of the most widely used error detection techniques for the data transmission. Before knowing about parity generator and checker, first let us see what is parity? In digital systems, when binary data is transmitted and processed, data may get corrupted due to some physical factors such as noise that can alter 0s (of data bits) to 1s and 1s to 0s. Hence, parity bit is added to the data to make number of 1s either odd or even. Thus it is used to detect errors during the transmission of binary data.

Parity Generator/Checker

A parity generator is a combinational logic circuit that generates the parity bit in the transmitter,where as Parity Checker is a circuit that checks the parity at the receiver end.Digital systems use a combined circuit or devices of parity generators and parity checkers to detect the single bit errors in the transmitted data. The sum of the data bits and parity bits can be even or odd.The basic principle of parity circuits is that sum of odd number of 1s is always 1 and sum of even number of 1s is always zero. The error detection and correction can be implemented by using XOR gates. To produce two bits sum, one XOR gate is sufficient whereas for adding three bits two XOR gates are required as shown below:

Parity Generator

Parity Generator is a combinational circuit that accepts the data and generates the additional bit that is to be transmitted with the bit stream. This additional or extra bit is called parity bit. In even parity bit, the parity bit is ‘0’ if there are even number of 1s in the data stream and the parity bit is ‘1’ if there are odd number of 1s in the data stream. Where as, In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream and the parity bit is ‘0’ if there are odd number of 1s in the data stream. We will discuss about both even and odd parity generators.

Even Parity Generator

Let us say that a 3-bit message is to be transmitted with an even parity bit. Let the three inputs be A, B and C that are applied to the circuit and output bit is the parity bit P. The total number of 1s must be even, to generate the even parity bit P. Below given is the truth table of even parity generator in which 1 is placed as parity bit in order to make all 1s as even when the number of 1s in the truth table is odd.

From the above truth table, using K-Map, the simplified expression of the parity bit can be written as:

We can implement the Even parity generator by using two XOR gates. The logic circuit of even parity generator with two XOR gates is given below. The three bit message along with the parity generated by this circuit which is transmitted to the receiving end where parity checker circuit checks for any error. 

Odd Parity Generator

Let us say that the 3-bit data is to be transmitted with an odd parity bit. Let the three inputs be A, B and C and P be the output parity bit. The total number of bits must be odd in order to generate the odd parity bit. Below given is the truth table. 1 is placed in the parity bit in order to make the total number of bits odd when the total number of 1s in the truth table is even.

The truth table of the odd parity generator can be simplified by using K-map and we can obtain the output parity bit expression for this generator circuit:

 

P = (A ⊕ B ⊕ C)’

The logic circuit designed by implementing the above boolean expressions:

Parity Checker

Parity checker is a logic circuit that checks whether errors are present or not in the transmission. This circuit can be an even parity checker or odd parity checker as per the parity generated at the transmission end. When this circuit is used as even parity checker, the number of input bits must always be even. When a parity error occurs, the ‘sum even’ output goes low and ‘sum odd’ output goes high. If this logic circuit is used as an odd parity checker, the number of input bits should be odd, but if an error occurs the ‘sum odd’ output goes low and ‘sum even’ output goes high.

Even Parity Checker

Let us consider that three input message along with even parity bit is generated at the transmitting end. The 4 bits are applied as input to the parity checker circuit which checks the possibility of error in the data. Since the data is transmitted with even parity, four bits received at circuit must have an even number of 1s. If any error occurs, the received message consists of odd number of 1s. The output of this parity checker is denoted by PEC (parity error check). Below given table represents the truth table for the even parity checker in which PEC = 1 if the error occurs, i.e., the 4 bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if the 4-bit message has even number of 1s.

The above truth table can be simplified using K-map as shown below and the boolean expression can be easily obtained:

Using the logic expression, we can easily implement the even parity checker by using three XOR gates. The logic circuit for even parity checker is given below:

Odd Parity Checker

Let us consider that a 3-bit message along with odd parity bit is transmitted at the transmitting end. Odd parity checker circuit receives the 4 bits and checks for any error in the data. If the total number of 1s in the data is odd, then it indicates no error. And if the total number of 1s is even, then it indicates the error as the data is transmitted with odd parity at transmitting end. Below given is the truth table for odd parity generator where PEC =1 if the 4-bit message received consists of even number of 1s (i.e. the error occurred) and PEC= 0 if the message contains odd number of 1s (i.e. no error).

The expression for the PEC in the above truth table can be simplified by K-map and the boolean expression can be obtained:

PEC = (((A ⊕ B)') ⊕ ((C ⊕ D)'))'                               [i.e. (A X-NOR B) X-NOR (C X-NOR D) ]

The logic circuit for the odd parity checker can be designed by using three X-NOR gates as shown below:

Advantages

• Its Simplicity
• It is easy to use 

Disadvantages

• It can only detect 1-bit error.
• It is unable to detect which bit is corrupted
• Data correction is not possible in Parity generator and checker, it can only be re-transmitted.

Applications

• Many hardware applications use parity generator and checker.
• Parity generator/checker is used in SCSI, i.e., Small Computer System Interface and also in PCI,i.e., Peripheral Component Interconnect.