Latches

 

Latches are special logic circuits, used to store data. A latch works as a storage device by holding the data through a feedback lane. It stores 1-bit of data. As latch has two stable states,i.e, active high and active low, so it is also known as a bistable multivibrator. 

When the enable is declared then latch can instantly change the stored data. Once the enable signal is activated, it constantly trials the inputs. The working of these circuits can be done in 2-states based on the enable signal being high or low. When the state of the latch circuit is active high state, then both the inputs are low and when the state of the latch circuit is an active low state, then both the inputs are high. Latches are level sensitive.

Types of Latches

Latches have various types. They can be classified as SR Latch, Gated S-R Latch, D latch, Gated D Latch, JK Latch, and T Latch.

SR Latch

An SR,i.e, Set/Reset latch is an asynchronous circuit that works separately for control signals by depending on the S-state & R-inputs. The SR-latch can be build using the NOR gate and as well as using the NAND gate. Below is a logic circuit of SR Latch that has used 2-NOR gates. The two inputs are exchanged as well as canceled. So it is called as SR-latch.

Whenever a high input is given to the S-line of the latch, then the output Q goes high. The output Q will stay high when the S-input goes low once more in the feedback process. And this is how the latch works as a memory device. Similarly, when a high input is given to the R-line of the latch, then the Q output goes low and Q’ goes high, then the memory of the latch will reset. When both of the inputs are low, then it stays in its earlier set state or reset state. The state transition table or truth table of the SR latch is shown below.

When both inputs are high at once, there is trouble: both the outputs are 0 which contradicts the fact that both the outputs should be each other's compliment. Hence, the latch will be in an undefined condition for an indefinite stage.

Gated SR Latch

A gated SR latch is just a simple extension to SR Latch. In some cases, we desire no change in the output even there is any change in output. Hence, in a gated SR latch, we have an Enable line that should be high so that information can be latched. It is like a control line but still, the latch is not a synchronous circuit due to the inputs which can alter the output even in the middle of an enable pulse. Following is a gated SR latch built using NOR gates.

The truth table of a gated SR latch is given below:

When input of the enable line is low, the latch is disabled. Therefore the Q & Q' outputs stay latched toward the earlier information. Now, when input of the enable line is high, the latch gets enabled. As the enable line is stated, the inputs and outputs remain same as that of SR latch. Sometimes, an enable line is a clock signal. 

D Latch

The data latch (or delay latch) is an expansion to SR latch. It can be easily constructed using two NOR gates. D latch overcomes the undefined condition of SR latch (when S=R=1). In it, we use an inverter i.e. NOT gate. Instead of input R, inverted S is the other input i.e. named as D. Following is the logic circuit of the D latch. 

The truth table of the D latch is given below:

The D-latch outputs the input of the D when the Enable line is high, otherwise, the output is the same as the previous one. This is the reason it is known as a transparent latch. When Enable is stated, then the latch is called transparent and signals spread straight through as if it isn’t present.

Gated D Latch

A gated D latch is constructed by changing a gated SR-latch. The only change in the gated SR-latch is that the input R must be modified to inverted S. Following given is the logic circuit of the gated D latch constructed through NOR Gates. 

The truth table of Gated D latch is given below:

If the clock is in active high state, the output latches whatever is on the input of the D. And, if the clock is in active low state, then the output will be of previous enable high.

This circuit can be safely used in any circuit, as it will never experience a race condition because the single D input is used and the other is its complement. Hence the outputs can never be the same. 

Advantages of Latches

• Latch circuits designs are more flexible.
• Digital latches are faster as they have no need to wait for a clock input signal, hence used in high-speed circuits. 
• They are small in size, hence require small area.
• Also, they consume less power.
• Latches are time borrowing and sharing. For example, if a circuit operation is not completed in the given time, they can borrow or share the required time to execute the operation.

Disadvantages of Latches

• Latches are less predictable. 
• As latches are level sensitive, there can be some chances of meta-stability.
• They are complicated to analyze the latch circuits and hence, the circuit needs to be tested.

Applications of Latches

• Latches have great use in digital systems and computing. These are the main storage units in computers and other digital systems.
• Latch being a single bit storage element, is used as a storage device in power gating circuits and clock.
• They can be used as pulse latches.
• In many asynchronous systems, D latches are used as I/O ports.
• Data latches are used to reduce the transit count in synchronous two-phase systems.